The present invention relates to a method for forming conductive lines and patterns and more particularly to a lithographic method for producing sub-half micron gate structures in electronic devices.
In the manufacture and production of electronic devices, and, more particularly, in the manufacture of semiconductor devices including high electron mobility transistors (HEMT) and metal-semiconductor field effect transistors (MESFET), there is a need for higher density devices for microelectronic applications. This demands development of techniques for defining ever finer features including conductive patterns for semiconductor interconnections such as Schottky barrier gate structures.
Various types of lithography are used for such microelectronic applications including conventional optical lithography, electron beam lithography (EBL) and x-ray lithography (XRL). It has been generally assumed that as the definition of sub-half micron features are desired in processes used for depositing metal patterns on semiconductors, the inherent limitations of optical lithography preclude its use in defining sub-half micron patterns. It has therefore been assumed that miniaturization requires the use of EBL and XRL techniques if such dimensions are to be achieved.
While EBL and XRL processes can achieve the line definitions desired for sub-half micron applications, these techniques require a major capital investment in equipment over that normally used in optical lithographic processes. Furthermore, when using EBL or XRL systems, there are other limitations in the applications of those methods which are time consuming and costly and thereby restrict their application in the production of integrated circuits.
By way of example, in EBL systems producing submicron structures in electron beam sensitized polymethylmethacrylate (PMMA) the procedure is time consuming and requires many hours to expose the fine line of patterns. This limits turn around time and increases the costs of production. Furthermore, in submicron structures only thin layers of PMMA can be used which severely limits the metal lifting capability for producing optimum low resistance Schottky barrier gates. Since such gates require a metal thickness in the order of 1 micron (10,000 .ANG.) and the PMMA layers are in the order of 2,000 .ANG. to 3,000 .ANG. thickness, the use of EBL requires elaborate multilevel resist structures and electroplating processes to achieve the metal thickness required for thick metal lifting.
Another difficulty that is encountered as the conducting line widths are decreased in microelectronic circuits relates to the conductive characteristics of the sub-half micron materials. Although small dimensions of the conductive depositions are desirable for optimizing device performance, of equal importance is the electrical resistance of the depositions, particularly in forming gate structures. Specifically, as the gate dimensions are decreased, the gate thickness must be increased exponentially to provide the low resistance required for optimum performance of the devices. In those processes using conventional EBL and XRL techniques, the cross sections formed by the lithographic process are often not sufficient to provide the thickness required to achieve the low resistance conduction characteristics needed for the electronic devices. There is therefore a continuing need for techniques which will allow additional reduction in the dimensions of the conductive structures using inexpensive equipment and procedures without significantly impacting the performance requirements of the resulting devices.
Accordingly, the present invention has been developed to overcome the above known and similar shortcomings and to provide a structure and technique for allowing the practice of optical lithography for producing sub-half micron conductive patterns in electronic devices.